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isolated sigma-delta modulator ad7400 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2011 analog devices, inc. all rights reserved. features 10 mhz clock rate second-order modulator 16 bits no missing codes 2 lsb inl typical at 16 bits 3.5 v/c maximum offset drift on-board digital isolator on-board reference low power operation: 18 ma maximum at 5.25 v ?40c to +105c operating range 16-lead soic package safety and regulatory approvals ul recognition 5000 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 891 v peak applications ac motor controls data acquisition systems a/d + opto-isolator replacements general description the ad7400 1 is a second-order, sigma-delta (-) modulator that converts an analog input signal to a high speed, 1-bit data stream with on-chip digital isolation based on analog devices, inc. i coupler? technology. the ad7400 operates from a 5 v power supply and accepts a differential input signal of 200 mv (320 mv full scale). the analog input is continuously sampled by the analog modulator, eliminating the need for external sample-and-hold circuitry. the input information is contained in the output stream as a density of ones with a data rate of 10 mhz. the original information can be reconstructed with an appropriate digital filter. the serial i/o can use a 5 v or a 3 v supply (v dd2 ). the serial interface is digitally isolated. high speed cmos, combined with monolithic air core transformer technology, means the on-chip isolation provides outstanding performance characteristics superior to alternatives such as optocoupler devices. the part contains an on-chip reference. the ad7400 is offered in a 16-lead soic and has an operating temperature range of ?40c to +105c. an external clock version, ad7401 , is also available. 1 protected by u.s. patents 5,952,849; 6,873,065; and 7,075,329. other patents pending. functional block diagram 04718-001 v in + v dd1 v dd2 v in ? - ? adc control logic ad7400 b u f t / h ref update gnd 1 gnd 2 mdat mclkout encode encode decode decode watchdog watchdog update figure 1.
ad7400 rev. d | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications .................................................................. 4 insulation and safety-related specifications............................ 5 regulatory information............................................................... 5 din v vde v 0884-10 (vde v 0884-10) insulation characteristics .............................................................................. 6 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical performance characteristics ..............................................9 terminology .................................................................................... 12 theory of operation ...................................................................... 13 circuit information.................................................................... 13 analog input ............................................................................... 13 differential inputs ...................................................................... 14 digital filter ................................................................................ 15 applications information .............................................................. 17 grounding and layout .............................................................. 17 evaluating the ad7400 performance ...................................... 17 insulation lifetime ..................................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 4/11rev. c to rev. d changes to dynamic input current parameter, table 1 ............. 3 1/11rev. b to rev. c changes to features section............................................................ 1 changes to input-to-output momentary withstand voltage parameter, table 3, ul column, table 4, and note 1, table 4.......... 5 changes to ordering guide...................................................................18 9/07rev. a to rev. b updated vde certification throughout ......................................1 changes to table 6.............................................................................7 12/06rev. 0 to rev. a changes to features ..........................................................................1 changes to table 6.............................................................................7 changes to analog input section................................................. 13 changes to figure 26...................................................................... 15 1/06revision 0: initial version
ad7400 rev. d | page 3 of 20 specifications v dd1 = 4.5 v to 5.25 v, v dd2 = 3 v to 5.5 v, v in + = ?200 mv to +200 mv, and v in ? = 0 v (single-ended); t a = t min to t max , f mclk = 10 mhz, tested with sinc 3 filter, 256 decimation rate, as defined by verilog code, unless otherwise noted. 1 table 1. parameter y version 1 , 2 unit test conditions/comments static performance resolution 16 bits min filter output truncated to 16 bits integral nonlinearity 3 15 lsb max ?40c to +85c; 2 lsb typical 25 lsb max >85c to 105c differential nonlinearity 3 0.9 lsb max guaranteed no missing codes to 16 bits offset error 3 0.5 mv max 50 v typ t a = 25c offset drift vs. temperature 3.5 v/c max ?40c to +105c 1 v/c typ offset drift vs. v dd1 120 v/v typ gain error 3 1 mv max gain error drift vs. temperature 23 v/c typ ?40c to +105c gain error drift vs. v dd1 110 v/v typ analog input input voltage range 200 mv min/mv max for specified performance; full range 320 mv dynamic input current 8 a max v in + = 400 mv, v in ? = 0 v 0.5 a typ v in + = v in ? = 0 v input capacitance 10 pf typ dynamic specifications v in + = 35 hz, 400 mv p-p sine signal-to-(noise + distortion) ratio (sinad) 3 70 db min ?40c to +85c 65 db min >85c to 105c 79 db typ signal-to-noise ratio (snr) 71 db min ?40c to +105c total harmonic distortion (thd) 3 ?88 db typ peak harmonic or spurious noise (sfdr) 3 ?88 db typ effective number of bits (enob) 3 11.5 bits isolation transient immunity 3 25 kv/s min 30 kv/s typ logic outputs output high voltage, v oh v dd2 ? 0.1 v min i o = ?200 a output low voltage, v ol 0.4 v max i o = +200 a power requirements v dd1 4.5/5.25 v min/v max v dd2 3/5.5 v min/v max i dd1 4 12 ma max v dd1 = 5.25 v i dd2 5 6 ma max v dd2 = 5.5 v 4 ma max v dd2 = 3.3 v 1 temperature range is ?40c to +85c. 2 all voltages are relative to their respective ground. 3 see the section. terminology 4 see . figure 14 5 see . figure 15
ad7400 rev. d | page 4 of 20 timing specifications v dd1 = 4.5 v to 5.25 v, v dd2 = 3 v to 5.5 v, t a = t max to t min , unless otherwise noted. 1 table 2. parameter limit at t min , t max unit description f mclkout 2 10 mhz typ master clock output frequency 9/11 mhz min/mhz max master clock output frequency t 1 3 40 ns max data access time after mclk rising edge t 2 3 10 ns min data hold time after mclk rising edge t 3 0.4 t mclkout ns min master clock low time t 4 0.4 t mclkout ns min master clock high time 1 sample tested during initial release to ensure compliance. 2 mark space ratio for clock output is 40/60 to 60/40. 3 measured with the load circuit of and defined as the time required for the output to cross 0.8 v or 2.0 v. figure 2 04718-002 200a i ol 200a i oh +1.6v to output pin c l 25pf figure 2. load circuit for digita l output timing specifications 04718-003 mclkout mdat t 1 t 2 t 4 t 3 figure 3. data timing
ad7400 rev. d | page 5 of 20 insulation and safety-related specifications table 3. parameter symbol value unit conditions input-to-output momentary withstand voltage v iso 5000 min v rms 1-minute duration minimum external air gap (clearance) l(i01) 7.46 min mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 8.1 min mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) regulatory information table 4. ul 1 csa vde 2 recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884-10 (vde v 0884- 10):2006-12 2 5000 v rms isolation voltage reinforced insulation per csa 60950-1-03 and iec 60950-1, 630 v rms maximum working voltage reinforced insulation per din v vde v 0884-10 (vde v 0884- 10):2006-12, 891v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul 1577, each ad7400 is proof tested by applying an insulation test voltage 6000 v rms for 1 second (curr ent leakage detection limit = 15 a). 2 in accordance with din v vde v 0884-10, each ad7400 is proof tested by applying an in sulation test voltag e 1671 v peak for 1 second (partial discharge detection limit = 5 pc).
ad7400 rev. d | page 6 of 20 din v vde v 0884-10 (vde v 0884-10) insulation characteristics this isolator is suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by means of protective circuits. table 5. description symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 300 v rms iCiv for rated mains voltage 450 v rms iCii for rated mains voltage 600 v rms iCii climatic classification 40/105/21 pollution degree (din vde 0110, table 1 ) 2 maximum working insulation voltage v iorm 891 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1671 v peak input-to-output test voltage, method a v pr after environmental test subgroup 1 1426 v peak v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc after input and/or safety test subgroup 2/3 1069 v peak v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage (transient overvoltage, t tr = 10 sec) v tr 6000 v peak safety-limiting values (maximum value allowed in the event of a failure, also see figure 4 ) case temperature t s 150 c side 1 current i s1 265 ma side 2 current i s2 335 ma insulation resistance at t s , v io = 500 v r s >10 9 case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side #1 side #2 04718-026 figure 4. thermal derating curve, dependence of safety-limiting values with case temperature per din v vde v 0884-10
ad7400 rev. d | page 7 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. all voltages are relative to their respective ground. table 6. parameter rating v dd1 to gnd 1 ?0.3 v to +6.5 v v dd2 to gnd 2 ?0.3 v to +6.5 v analog input voltage to gnd 1 ?0.3 v to v dd1 + 0.3 v output voltage to gnd 2 ?0.3 v to v dd2 + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature 150c soic package ja thermal impedance 89.2c/w jc thermal impedance 55.6c/w resistance (input-to-output), r i-o 10 12 capacitance (input-to-output), c i-o 2 1.7 pf typ pb-free temperature, soldering reflow 260 (+0)c esd 1.5 kv 1 transient currents of up to 100 ma do not cause scr to latch-up. 2 f = 1 mhz. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 7. maximum continuous working voltage 1 parameter max unit constraint ac voltage, bipolar waveform 565 v pk 50-year minimum lifetime ac voltage, unipolar waveform 891 v pk maximum csa/vde approved working voltage dc voltage 891 v maximum csa/vde approved working voltage 1 refers to continuous voltage magni tude imposed across the isolation barrier. see the insulation lifetime section for more details. esd caution
ad7400 rev. d | page 8 of 20 pin configuration and fu nction descriptions 04718-004 nc = no connect ad7400 top view (not to scale) v dd1 v dd2 v in + v in ? gnd 2 gnd 2 v dd1 g nd 1 1 2 3 nc 4 nc 5 nc mclkout nc 16 15 14 nc 6 7 8 mdat nc 11 10 9 13 12 figure 5. pin configuration table 8. pin function descriptions pin no. mnemonic description 1, 7 v dd1 supply voltage. 4.5 v to 5.25 v. this is the supply voltage for the isolated side of the ad7400 and is relative to gnd 1 . 2 v in + positive analog input. specified range of 200 mv. 3 v in ? negative analog input. no rmally connected to gnd 1 . 4 to 6, 10, 12, 15 nc no connect. 8 gnd 1 ground 1. this is the ground reference point for all circuitry on the isolated side. 9, 16 gnd 2 ground 2. this is the ground reference point for all circuitry on the nonisolated side. 11 mdat serial data output. the single bit modulator output is supplied to this pin as a serial data stream. the bits are clocked out on the rising edge of the mclkout output and valid on the following mclkout rising edge. 13 mclkout master clock logic output. 10 mhz typical. the bit stream from the modulator is valid on the rising edge of mclkout. 14 v dd2 supply voltage. 3 v to 5.5 v. this is the supply vo ltage for the nonisolated side and is relative to gnd 2 .
ad7400 rev. d | page 9 of 20 100 0 20 10 30 40 50 60 70 80 90 1000 200 300 400 500 600 700 800 900 1000 04718-005 typical performance characteristics t a = 25c, using a 20 khz brick wall filter, unless otherwise noted. supply ripple frequency (khz) psrr (db) 200mv p-p sinewave on v dd1 no decoupling v dd1 = v dd2 = 4.5v to 5.25v figure 6. psrr vs. supply ripple freq uency without supply decoupling (1 mhz filter used) 0 ? 90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 4000 3500 3000 2500 2000 1500 1000 500 04718-006 input frequency (hz) sinad (db) v dd1 = v dd2 = 4.5v v dd1 = v dd2 = 5.25v v dd1 = v dd2 = 5v figure 7. sinad vs. analog input frequency for various supply voltages frequency (khz) ?180 ?160 ?140 02 1816141210 8642 04718-007 (db) 0 ?20 ?120 ?100 ?80 ?60 ?40 0 8192 point fft f in = 35hz sinad = 79.6991db thd = ?92.6722db decimation by 256 figure 8. typical fft, 200 mv range (using sinc 3 filter, 256 decimation rate) 0 ? 90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0.195 0.315 0.215 0.235 0.255 0.275 0.295 04718-008 input amplitude (v) sinad (db) v dd1 =v dd2 =5v figure 9. sinad vs. v in code dnl error (lsb) 0.5 ?0.4 ?0.3 ?0.2 0 ?0.1 0.1 0.2 0.3 0.4 04718-009 0 60000 50000 40000 30000 20000 10000 v in + = ?200mv to +200mv v in ? = 0v figure 10. typical dnl, 200 mv range (using sinc 3 filter, 256 decimation rate) code 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 0 60000 50000 40000 30000 20000 10000 04718-010 v in + = ?200mv to +200mv v in ?= 0v inl error (lsb) figure 11. typical inl, 200 mv range (using sinc 3 filter, 256 decimation rate)
ad7400 rev. d | page 10 of 20 ?200 100 50 ?50 0 ?100 ?150 ?45?35?25?15?5 5 152535455565758595105 04718-011 temperature (c) offset (v) v dd1 =v dd2 =4.5v v dd1 =v dd2 = 5.25v v dd1 =v dd2 =5v figure 12. offset drift vs. temper ature for various supply voltages v dd1 = v dd2 = 4.5v ?0.20 0.20 0.15 ?0.05 0 0.05 0.10 ?0.10 ?0.15 ?45?35?25?15?5 5 152535455565758595105 04718-012 temperature (c) gain (%) v dd1 = v dd2 = 5v v dd1 = v dd2 = 5.25v figure 13. gain error drift vs. temperature for various supply voltages 0.0089 0.0090 0.0091 0.0092 0.0093 0.0094 0.0095 0.0096 0.0097 0.0098 0.0099 ?0.34 ?0.30 ?0.26 ?0.22 ?0.18 ?0.14 ?0.10 ?0.06 ?0.02 0.02 0.30 0.06 0.10 0.14 0.18 0.22 0.26 0.34 04718-013 v in dc input voltage (v) i dd1 (a) v dd1 = v dd2 = 5v t a = +85c t a = +25c t a = ?40c figure 14. i dd1 vs. v in at various temperatures 0.0030 0.0031 0.0032 0.0033 0.0034 0.0035 0.0036 ?0.34 ?0.30 ?0.26 ?0.22 ?0.18 ?0.14 ?0.10 ?0.06 ?0.02 0.02 0.30 0.06 0.10 0.14 0.18 0.22 0.26 0.34 04718-014 v in dc input voltage (v) i dd2 (a) v dd1 = v dd2 = 5v i d d 2 @ + 8 5 c i d d 2 @ ? 4 0 c i d d 2 @ + 2 5 c figure 15. i dd2 vs. v in at various temperatures v in + dc input (v) i in (a) v dd1 = v dd2 = 4.5v to 5.25v 9 6 3 0 ?3 ?6 ?9 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.35 04718-015 figure 16. i in vs. v in + dc input ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 1 10 100 1000 10000 0.1 04718-016 ripple frequency (khz) cmrr (db) figure 17. cmrr vs. common-mode ripple frequency
ad7400 rev. d | page 11 of 20 1.0 0.8 0.6 0.4 0.2 0 ?0.30 ?0.20 ?0.25 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 04718-017 v in dc input (v) noise (mv) bandwidth = 100khz figure 18. rms noise voltage vs. v in dc input 11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 9.2 9.0 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 95 105 04718-024 temperature (c) mclkout (mhz) v dd1 =v dd2 =4.5v v dd1 =v dd2 =5v v dd1 =v dd2 =5.25v figure 19. mclkout vs. temp erature for various supplies
ad7400 rev. d | page 12 of 20 terminology differential nonlinearity differential nonlinearity is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are specified negative full scale, ?200 mv (v in + ? v in ?), code 12,288 for the 16-bit level, and specified positive full scale, +200 mv (v in + ? v in ?), code 53,248 for the 16-bit level. offset error offset error is the deviation of the midscale code (code 32,768 for the 16-bit level) from the ideal v in + ? v in ? (that is, 0 v). gain error gain error includes both positive full-scale gain error and negative full-scale gain error. positive full-scale gain error is the deviation of the specified positive full-scale code (53,248 for the 16-bit level) from the ideal v in + ? v in ? (+200 mv) after the offset error is adjusted out. negative full-scale gain error is the deviation of the specified negative full-scale code (12,288 for the 16-bit level) from the ideal v in + ? v in ? (?200 mv) after the offset error is adjusted out. gain error includes reference error. signal-to-(noise + distortion) ratio (sinad) this ratio is the measured ratio of signal-to-(noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal-to-(noise + distortion) = (6.02n + 1.76) db therefore, for a 12-bit converter, this is 74 db. effective number of bits (enob) the enob is defined by enob = ( sinad ? 1.76)/6.02 total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the ad7400, it is defined as 1 65432 v vvvvv thd 22222 log20)db( ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. common-mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at 200 mv frequency, f, to the power of a 200 mv p-p sine wave applied to the common-mode voltage of v in + and v in ? of frequency f s , expressed as cmrr (db) = 10log( pf/pf s ) where: pf is the power at frequency f in the adc output. pf s is the power at frequency f s in the adc output. power supply rejection ratio (psrr) variations in power supply affect the full-scale transition but not converter linearity. psrr is the maximum change in the specified full-scale (200 mv) transition point due to a change in power supply voltage from the nominal value (see figure 6 ). isolation transient immunity the isolation transient immunity specifies the rate of rise/fall of a transient pulse applied across the isolation boundary beyond which clock or data is corrupted. (it was tested using a transient pulse frequency of 100 khz.)
ad7400 rev. d | page 13 of 20 theory of operation circuit information the ad7400 isolated - modulator converts an analog input signal into a high speed (10 mhz typical), single-bit data stream; the time average of the modulators single-bit data is directly proportional to the input signal. figure 22 shows a typical application circuit where the ad7400 is used to provide isolation between the analog input, a current sensing resistor, and the digital output, which is then processed by a digital filter to provide an n-bit word. analog input the differential analog input of the ad7400 is implemented with a switched capacitor circuit. this circuit implements a second-order modulator stage that digitizes the input signal into a 1-bit output stream. the sample clock (mclkout) provides the clock signal for the conversion process as well as the output data-framing clock. this clock source is internal on the ad7400. the analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. a digital stream that accurately represents the analog input over time appears at the output of the converter (see figure 20 ). 04718-019 modulator output +fs analog input ?fs analog input analog input figure 20. analog input vs. modulator output a differential signal of 0 v results (ideally) in a stream of 1s and 0s at the mdat output pin. this output is high 50% of the time and low 50% of the time. a differential input of 200 mv pro- duces a stream of 1s and 0s that are high 81.25% of the time. a differential input of ?200 mv produces a stream of 1s and 0s that are high 18.75% of the time. a differential input of 320 mv results in a stream of, ideally, all 1s. this is the absolute full-scale range of the ad7400, while 200 mv is the specified full-scale range, as shown in table 9 . table 9. analog input range analog input voltage input full-scale range +640 mv positive full scale +320 mv positive specified input range +200 mv zero 0 mv negative specified input range ?200 mv negative full scale ?320 mv to reconstruct the original information, this output needs to be digitally filtered and decimated. a sinc 3 filter is recommended because this is one order higher than that of the ad7400 modulator. if a 256 decimation rate is used, the resulting 16-bit word rate is 39 khz, assuming a 10 mhz internal clock frequency. figure 21 shows the transfer function of the ad7400 relative to the 16-bit output. 04718-020 65535 53248 specified range analog input adc code 12288 ?320mv ?200mv +200mv +320mv 0 figure 21. filtered and decimated 16-bit transfer characteristic 04718-018 - ? mod/ encoder input current nonisolated 5v/3v isolated 5v v dd1 r shunt v in + v in ? gnd 1 v dd gnd v dd2 mdat mdat sinc 3 filter ad7400 mclkout sdat cs scl k mclk gnd 2 decoder decoder + encoder figure 22. typical application circuit
ad7400 rev. d | page 14 of 20 differential inputs the analog input to the modulator is a switched capacitor design. the analog signal is converted into charge by highly linear sampling capacitors. a simplified equivalent circuit diagram of the analog input is shown in figure 23 . a signal source driving the analog input must be able to provide the charge onto the sampling capacitors every half mclkout cycle and settle to the required accuracy within the next half cycle. a b 1k? v in ? a b b b 1k? v in + 2pf 2pf a a mclkout 0 4718-027 figure 23. analog input equivalent circuit because the ad7400 samples the differential voltage across its analog inputs, low noise performance is attained with an input circuit that provides low common-mode noise at each input. the amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the ad7400. when a capacitive load is switched onto the output of an op amp, the amplitude momentarily drops. the op amp tries to correct the situation and, in the process, hits its slew rate limit. this nonlinear response, which can cause excessive ringing, can lead to distortion. to remedy the situation, a low-pass rc filter can be connected between the amplifier and the input to the ad7400. the external capacitor at each input aids in supplying the current spikes created during the sampling process, and the resistor isolates the op amp from the transient nature of the load. the recommended circuit configuration for driving the differential inputs to achieve best performance is shown in figure 24 . a capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by one input to be effectively supplied by the other input. the series resistor again isolates any op amp from the current spikes created during the sampling process. recommended values for the resistors and capacitor are 22 and 47 pf, respectively. r v in ? r v in + c ad7400 04718-028 figure 24. differential input rc network
ad7400 rev. d | page 15 of 20 digital filter a sinc 3 filter is recommended for use with the ad7400. this filter can be implemented on an fpga or a dsp. the following verilog code provides an example of a sinc 3 filter implementation on a xilinx? spartan-ii 2.5 v fpga. this code can possibly be compiled for another fpga, such as an altera? device. note that the data is read on the negative clock edge in this case, although it can be read on the positive edge if preferred. figure 28 shows the effect of using different decimation rates with various filter types. /*`data is read on negative clk edge*/ module dec256sinc24b(mdata1, mclk1, reset, data); input mclk1; /*used to clk filter*/ input reset; /*used to reset filter*/ input mdata1; /*ip data to be filtered*/ output [15:0] data; /*filtered op*/ integer location; integer info_file; reg [23:0] ip_data1; reg [23:0] acc1; reg [23:0] acc2; reg [23:0] acc3; reg [23:0] acc3_d1; reg [23:0] acc3_d2; reg [23:0] diff1; reg [23:0] diff2; reg [23:0] diff3; reg [23:0] diff1_d; reg [23:0] diff2_d; reg [15:0] data; reg [7:0] word_count; reg word_clk; reg init; /*perform the sinc action*/ always @ (mdata1) if(mdata1==0) ip_data1 <= 0; /* change from a 0 to a -1 for 2's comp */ else ip_data1 <= 1; /*accumulator (integrator) perform the accumulation (iir) at the speed of the modulator. 04718-021 mclkout ip_data1 acc1+ acc2+ acc3 + z + z + z figure 25. accumulator z = one sample delay mclkout = modulators conversion bit rate */ always @ (negedge mclk1 or posedge reset) if (reset) begin /*initialize acc registers on reset*/ acc1 <= 0; acc2 <= 0; acc3 <= 0; end else begin /*perform accumulation process*/ acc1 <= acc1 + ip_data1; acc2 <= acc2 + acc1; acc3 <= acc3 + acc2; end /*decimation stage (mclkout/ word_clk) */ always @ (posedge mclk1 or posedge reset) if (reset) word_count <= 0; else word_count <= word_count + 1; always @ (word_count) word_clk <= word_count[7]; /*differentiator (including decimation stage) perform the differentiation stage (fir) at a lower speed. w ord_clk acc3 diff1 diff3 + ? + ? diff2 z ?1 ? + ? z ?1 z ?1 0 4718-022 figure 26. differentiator z = one sample delay word_clk = output word rate */
ad7400 rev. d | page 16 of 20 always @ (posedge word_clk or posedge reset) if(reset) begin acc3_d2 <= 0; diff1_d <= 0; diff2_d <= 0; diff1 <= 0; diff2 <= 0; diff3 <= 0; end else begin diff1 <= acc3 - acc3_d2; diff2 <= diff1 - diff1_d; diff3 <= diff2 - diff2_d; acc3_d2 <= acc3; diff1_d <= diff1; diff2_d <= diff2; end /* clock the sinc output into an output register 04718-023 word_clk data diff3 figure 27. clocking sinc outp ut into an output register word_clk = output word rate */ always @ (posedge word_clk) begin data[15] <= diff3[23]; data[14] <= diff3[22]; data[13] <= diff3[21]; data[12] <= diff3[20]; data[11] <= diff3[19]; data[10] <= diff3[18]; data[9] <= diff3[17]; data[8] <= diff3[16]; data[7] <= diff3[15]; data[6] <= diff3[14]; data[5] <= diff3[13]; data[4] <= diff3[12]; data[3] <= diff3[11]; data[2] <= diff3[10]; data[1] <= diff3[9]; data[0] <= diff3[8]; end endmodule 80 70 60 50 40 30 20 10 0 90 10 100 1k 1 04718-025 decimation rate snr (db) sinc 3 sinc 2 sinc 1 figure 28. snr vs. decimation rate for different filter types
ad7400 rev. d | page 17 of 20 applications information grounding and layout supply decoupling with a value of 100 nf is strongly recom- mended on both v dd1 and v dd2 . decoupling on one or both v dd1 pins does not significantly affect performance. in applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. furthermore, the board layout should be designed so that any coupling that occurs equally affects all pins on a given component side. failure to ensure this may cause voltage differentials between pins to exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. any decoupling used should be placed as close to the supply pins as possible. series resistance in the analog inputs should be minimized to avoid any distortion effects, especially at high temperatures. if possible, equalize the source impedance on each analog input to minimize offset. beware of mismatch and thermocouple effects on the analog input pcb tracks to reduce offset drift. evaluating the ad7400 performance a simple standalone ad7400 evaluation board is available with split ground planes and a board split beneath the ad7400 package to ensure isolation. this board allows access to each pin on the device for evaluation purposes. external supplies and all other circuitry (such as a digital filter) must be provided by the user. insulation lifetime all insulation structures, subjected to sufficient time and/or voltage, are vulnerable to breakdown. in addition to the testing performed by the regulatory agencies, analog devices has carried out an extensive set of evaluations to determine the lifetime of the insulation structure within the ad7400. these tests subjected populations of devices to continuous cross-isolation voltages. to accelerate the occurrence of failures, the selected test voltages were values exceeding those of normal use. the time-to-failure values of these units were recorded and used to calculate acceleration factors. these factors were then used to calculate the time to failure under normal operating conditions. the values shown in table 7 are the lesser of the following two values: ? the value that ensures at least a 50-year lifetime of continuous use ? the maximum csa/vde approved working voltage it should also be noted that the lifetime of the ad7400 varies according to the waveform type imposed across the isolation barrier. the i coupler insulation structure is stressed differently depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 29 , figure 30 , and figure 31 illustrate the different isolation voltage waveforms. 0v rated pe a k v oltage 04718-029 figure 29. bipolar ac waveform 0v r a ted pe a k v oltage 04718-030 figure 30. unipolar ac waveform 0v r a ted pe a k v oltage 04718-031 figure 31. dc waveform
ad7400 rev. d | page 18 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 32. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option AD7400YRWZ ?40c to +105c 16-lead standard small outline package [soic_w] rw-16 AD7400YRWZ-reel ?40c to +105c 16-lead standard small outline package [soic_w] rw-16 AD7400YRWZ-reel7 ?40c to +105c 16-lead standard small outline package [soic_w] rw-16 eval-ad7400edz evaluation board eval-ced1z development board 1 z = rohs compliant part.
ad7400 rev. d | page 19 of 20 notes
ad7400 rev. d | page 20 of 20 notes ?2006C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04718-0-4/11(d)

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